MT48H16M16LFF-8 데이터 시트보기 (PDF) - Micron Technology
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MT48H16M16LFF-8 Datasheet PDF : 58 Pages
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ADVANCE
256Mb: x16
MOBILE SDRAM
SINGLE WRITE – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP 2
NOP 2
PRECHARGE
NOP
ACTIVE
NOP
DQM /
DQML, DQMU
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m 3
DISABLE AUTO PRECHARGE
BANK
ALL BANKS
SINGLE BANK
BANK
ROW
BANK
tDS tDH
DQ
DIN m
tRCD
t WR 4
tRP
tRAS
tRC
DON’T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. PRECHARGE command not allowed else tRAS would be violated.
3. x16: A9, A11 and A12 = “Don’t Care”
4. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single write
tWR has been increased to meet minimum tRAS requirement.
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
-8
MIN MAX
1
2.5
3
3
8
10
20
1
2.5
-10
MIN MAX
1
2.5
3
3
10
12
25
1
2.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
SYMBOL*
tCMH
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
-8
MIN MAX
1
2.5
1
2.5
48 120,000
80
20
20
15
-10
MIN MAX UNITS
1
ns
2.5
ns
1
ns
2.5
ns
50 120,000 ns
100
ns
20
ns
20
ns
15
ns
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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