HI3197JCQ 데이터 시트보기 (PDF) - Intersil
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HI3197JCQ Datasheet PDF : 25 Pages
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HI3197
Description of Operation
The HI3197 has four types of operation modes to support
various applications. The operation mode is set by switching
the function setting pins (C1, C2 and C3).
The HI3197 can input data divided into two systems: A (DA0
to DA9) and B (DB0 to DB9), internally multiplex the data,
and output it as an analog signal, making it possible to halve
the data rate. This lets the HI3197 support the TTL data
input level in contrast to the ECL data input level for
conventional high-speed D/A converters. The clock signal
and reset signal input levels can be selected from either TTL
or PECL according to the application. (However, setting both
signals to either TTL or PECL input level is recommended.)
MUX.1A Mode
Set C1, C2 and C3 all Low for this mode.
In MUX.1A mode, the frequency of the clock input from the
clock input pin is halved internally, and the 1/2 frequency-
divided signal is output at TTL level from the DlV2OUT pin.
Data synchronized with the DlV2OUT signal (the signal
output from the DlV2OUT pin) can be obtained by operating
the HI3197 front-end system with the DlV2OUT signal. The
timing at which the data output delay of the HI3197 front-end
system matches with the hold time during HI3197 data input
can be easily set by inputting this synchronized data to the
data input pins and the DlV2OUT signal to the DlV2lN pin.
The data can be divided and input to two systems: A (DA0 to
DA9) and B (DB0 to DB9), internally multiplexed, and
extracted as analog output.
When using the multiple HI3197 in MUX.1A mode, the start
timing of the 1/2 frequency-divided clocks becomes out of
phase, producing operation such as that shown in Figure 7.
As a countermeasure, the MUX.1A mode has a function that
matches the start timing of the 1/2 frequency-divided clocks
with the reset signal. When using a PECL level reset signal,
input the reset signal to Pins 23 and 24 (RESETP/E,
RESETN/E) and leave Pin 22 (RESET/T) open. When using
a TTL level reset signal, input the reset signal to Pin 22
(RESET/T) and leave Pins 23 and 24 (RESETP/E,
RESETN/E) open. The reset polarity can be switched by the
R POLARITY pin (Pin 39). When the R POLARITY pin is
High or open, reset is active Low; when Low, reset is active
High. See Figure 7 for the detailed timing.
TABLE 2. OPERATING MODES
MODE
C1
C2
C3
CLK IN DATA IN AOUT
(MSPS) (Mbps) (Mbps)
DIV2OUT PIN
DESCRIPTION OF OPERATION
MUX.1A
0
0
0
125
MUX.1B 0
0
1
125
62.5
62.5
125 Outputs CLK/2 at TTL Level MUX Operation by the Internal CLK/2
125 High Impedance
MUX Operation by the Internal CLK/2
MUX.2
0
1
0
125
62.5
125 High Impedance
MUX Operation by DIV2IN
SELE.A
1
0
0
125
125
125 High Impedance
D/A Conversion of Side A Data Input
SELE.B
1
1
0
125
125
125 High Impedance
D/A Conversion of Side B Data Input
CLOCK INPUT
tD - DIV
(DIV2OUT SIGNAL)
CLOCK INPUT PIN
1/2
DIV2OUT PIN
DIV2IN PIN
HI3197
FRONT-END
SYSTEM
10-BIT
10-BIT
10-BIT DATA A
10-BIT DATA B
DA0 TO DA9
DB0 TO DB9
DATA INPUT PINS
FRONT-END SYSTEM DATA OUTPUT DELAY
II
HI3197 DATA INPUT HOLD TIME
FIGURE 7A. MUX.1A
HI3197 (MUX.1A MODE)
14
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