HI3197JCQ 데이터 시트보기 (PDF) - Intersil

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HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

HI3197

Block Diagram and Timing Charts (Continued)

CLK

DIV2IN

RQ

DQ

CLK/2

(INTERNAL)

INPUT DATA A

INPUT DATA B

A

INPUT LATCH A

B

INPUT LATCH B

LATCH

LATCH

MUX

LATCH

FIGURE 13A. BLOCK DIAGRAM (MUX.2 MODE)

DAC

ANALOG OUT

tPW1 tPW0

tPD (B)

tPD (A)

CLK

DIV1IN

tS-DIV

M/S DATA A

N-2

M/S DATA B

N-1

tH-DIV

0

1

2

tS

tH

N

N+2

N+1

N+3

3

N+4

N+5

N+6

N+7

N+8

N+9

N+5

tDO

N+3

N+4

N+2

N+1

N

tDO

FIGURE 13B. TIMING MODE (MUX.2 MODE)

NOTE: In MUX.2 mode, the 1/2 frequency-divided clock signal (DlV2lN) and Data A and Data B, which are synchronized with DlV2lN, are provided

simultaneously. These signals are internally multiplexed and the resulting signal can be analog output.

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