HI3197JCQ 데이터 시트보기 (PDF) - Intersil

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HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

HI3197

Block Diagram and Timing Charts

CLK

RESET

DIV2OUT

DIV2IN

RQ

DQ

CLK/2

(INTERNAL)

INPUT DATA A

INPUT LATCH A

INPUT DATA B

INPUT LATCH B

LATCH

LATCH

MUX

LATCH

DAC

ANALOG OUT

FIGURE 11A. BLOCK DIAGRAM (MUX.1A MODE)

CLK

tS-RST

RESET

CLK/2

(INTERNAL)

DIV2OUT

TO

DIV2IN

INPUT DATA A

tPW1 tPW0

ACTIVE HIGH

tH-RST

ACTIVE LOW

tD-DIV

2t-tM

N$

N$

INPUT DATA B

N$

N$

tPD

tPD (A)

0

1

2

3

4

5

tM

tS

N

N+1

tH

N+2

N+3

N+4

N+5

N$

N$

tDO

N+1

N

N$

N$

tDO

FIGURE 11B. TIMING CHART (MUX.1A MODE)

PECL

CLK

±1/2 LSB

2.0V

TTL

0.8V

2.0V

0.8V

ANALOG

OUTPUT

±1/2 LSB

tDO tSET

FIGURE 11C. TIMING JUDGMENT POINTS

NOTE: In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the

clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be output at TTL level (D1V201.~). CLK/2 can be reset by the reset

signal.

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