HI3197JCQ 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

HI3197

Block Diagram and Timing Charts (Continued)

CLK

RESET

RQ

DQ

CLK/2

(INTERNAL)

INPUT DATA A

INPUT DATA B

INPUT LATCH A

INPUT LATCH B

MUX

LATCH

FIGURE 12A. BLOCK DIAGRAM (MUX.1B MODE)

DAC

ANALOG OUT

tPW1 tPW0

tPD (B)

tPD (A)

CLK

RESET

(ACTIVE HIGH)

CLK/2

(INTERNAL)

INPUT DATA A

INPUT DATA B

tS-RST tH-RST

0

(ACTIVE HIGH)

(ACTIVE LOW)

D-FF OUT

N-2

tS tH

N

N-1

N+1

1

2

3

N+2

N+3

tDO

N+4

N+5

N+6

N+7

N+8

N+9

N+5

N+4

N+3

N+2

N+1

N

tDO

FIGURE 12B. TIMING CHART (MUX.1B MODE)

NOTE: In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the

clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal.

19

Share Link: