HI3197JCQ 데이터 시트보기 (PDF) - Intersil

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HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

CLK

HI3197

CLK DIV2OUT

HI3197

CLKDIV2OUT

HI3197

CLK

DIV2OUT

DIV2OUT

FIGURE 7B. MUX.1A EXAMPLE WHEN NOT USING THE RESET SIGNAL

CLK

RESET

SIGNAL

HI3197

CLK DIV2OUT

RESET

HI3197

CLKDIV2OUT

RESET

CLK

RESET SIGNAL

(WHEN ACTIVE LOW)

DIV2OUT

DIV2OUT

FIGURE 7C. MUX.1A EXAMPLE WHEN USING THE RESET SIGNAL

FIGURE 7. MUX.1A MODE

MUX.1B Mode

Set C1 and C2 Low and C3 High for this mode.

In MUX.1B mode, the frequency of the clock input from the

clock input pin is halved internally, and the data is loaded by

this 1/2 frequency-divided signal. The 1/2 frequency-divided

signal cannot be observed at this time, so the data is actually

loaded by observing the clock and reset signals to estimate

the rising edge of the internally 1/2 frequency-divided signal.

The data can be divided and input to two systems: A (DA0 to

DA9) and B (DB0 to DB9). The data is internally multiplexed,

then the system A data is output as an analog signal with a

2-clock pipeline delay, and the system B data as an analog

signal with a 3-clock pipeline delay after loading by the clock.

Like MUX.1A mode, when using the multiple HI3197 in

MUX.1B mode, the start timing of the 1/2 frequency-divided

clocks becomes out of phase, producing operation such as

that shown in the example below. As a countermeasure, the

MUX.1B mode also has a function that matches the start

timing of the 1/2 frequency-divided clocks with the reset

signal. When using a PECL level reset signal, input the reset

signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave

Pin 22 (RESET/T) open. When using a TTL level reset signal,

input the reset signal to Pin 22 (RESET/T) and leave Pins 23

and 24 (RESETP/E, RESETN/E) open. The reset polarity can

be switched by the R POLARITY pin (Pin 39). When the R

POLARITY pin is High or open, reset is active Low; when

Low, reset is active High. See Figure 8 for the detailed timing.

15

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