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SST49LF020A

2 Mbit LPC Flash

Silicon Storage Technology 

2 Mbit LPC Flash

SST49LF020A

CE#

The CE# pin, enables and disables the SST49LF020A,

controlling read and write access of the device. To enable

the SST49LF020A, the CE# pin must be driven low one

clock cycle prior to LFRAME# being driven low. The device

will enter standby mode when internal Write operations are

completed and CE# is high.

LFRAME#

The LFRAME# signifies the start of a (frame) bus cycle or

the termination of an undesired cycle. Asserting LFRAME#

for one or more clock cycle and driving a valid START value

on LAD[3:0] will initiate device operation. The device will

enter standby mode when internal operations are com-

pleted and LFRAME# is high.

TBL#, WP#

The Top Boot Lock (TBL#) and Write Protect (WP#) pins

are provided for hardware write protection of device mem-

ory. The TBL# pin is used to Write-Protect 4 boot sectors

(16 KByte). The WP# pin write protects the remaining sec-

tors in the flash memory.

An active low signal at the TBL# pin prevents Program and

Erase operations of the top boot sectors. When TBL# pin is

held high, the write protection of the top boot sectors is dis-

abled. The WP# pin serves the same function for the

remaining sectors of the device memory. The TBL# and

WP# pins write protection functions operate independently

of one another.

Data Sheet

Both TBL# and WP# pins must be set to their required pro-

tection states prior to starting a Program or Erase opera-

tion. A logic level change occurring at the TBL# or WP# pin

during a Program or Erase operation could cause unpre-

dictable results.

INIT#, RST#

A VIL on INIT# or RST# pin initiates a device reset. INIT#

and RST# pins have the same function internally. It is

required to drive INIT# or RST# pins low during a system

reset to ensure proper CPU initialization. During a Read

operation, driving INIT# or RST# pins low deselects the

device and places the output drivers, LAD[3:0], in a high-

impedance state. The reset signal must be held low for a

minimal duration of time TRSTP. A reset latency will occur if

a reset procedure is performed during a Program or Erase

operation. See Table 17, Reset Timing Parameters for

more information. A device reset during an active Program

or Erase will abort the operation and memory contents may

become invalid due to data being altered or corrupted from

an incomplete Erase or Program operation.

System Memory Mapping

The LPC interface protocol has address length of 32-bit or

4 GByte. The SST49LF020A will respond to addresses in

the range as specified in Table 4.

Refer to “Multiple Device Selection” section for more detail

on strapping multiple SST49LF020A devices to increase

memory densities in a system and “Registers” section on

valid register addresses.

TABLE 4: Address Decoding Range

ID Strapping

Device #0 - 15

Device Access

Memory Access

Register Access

Address Range

FFFF FFFFH : FFC0 0000H

FFBF FFFFH : FF80 0000H

Memory Size

4 MByte

4 MByte

T4.0 1206

©2006 Silicon Storage Technology, Inc.

11

S71206-08-000

5/06

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