CDP68HC68T1(1997) 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

CDP68HC68T1
(Rev.:1997)

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

CDP68HC68T1

Power Sense

This bit is used to enable the line input pin to sense a power

failure. It is set high for this function. When power sense is

selected, the input to the 50Hz to 60Hz prescaler is discon-

nected. Therefore, crystal operation is required when power

sense is enabled. An interrupt is generated when a power

failure is sensed and the power sense and Interrupt True bit

in the Status Register are set. When power sense is acti-

vated, a “0” must be written to this location followed by a “1”

to re-enable power sense.

Alarm

The output of the alarm comparator is enabled when this bit

is set high. When a comparison occurs between the sec-

onds, minutes and hours time and alarm counters, the inter-

rupt output is activated. When loading the time counters, this

bit should be set low to avoid a false interrupt. This is not

required when loading the alarm counters. See Pin Func-

tions, INT for explanation of alarm delay.

Periodic Select

The value in these 4 bits will select the frequency of the peri-

odic output. (See Table 2).

INTERRUPT CONTROL REGISTER (Write/Read) - Address 32H

D7

D6

D5

D4

D3

D2

D1

D0

WATCHDOG

POWER

DOWN

POWER

SENSE

ALARM

PERIODIC SELECT

NOTE: All bits are reset by power-on reset.

D0 - D3 VALUE

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

TABLE 2. PERIODIC INTERRUPT OUTPUT

PERIODIC INTERRUPT

OUTPUT FREQUENCY

FREQUENCY TIME BASE

XTAL

LINE

Disable

2048Hz

X

1024Hz

X

512Hz

X

256Hz

X

128Hz

X

64Hz

X

50 or 60Hz

X

32Hz

X

16Hz

X

8Hz

X

4Hz

X

2Hz

X

X

1Hz

X

X

Minute

X

X

Hour

X

X

Day

X

X

11

Share Link: