UC1608XFAC 데이터 시트보기 (PDF) - Unspecified
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UC1608XFAC Datasheet PDF : 42 Pages
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ULTRACHIP
High-Voltage Mixed-Signal IC
©1999-2002
COMMAND DESCRIPTION
(1) Write data to display memory
Action
Write data
(2) Read data to display memory
Action
Read data
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
10
8bits data write to SRAM
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
11
8bits data from SRAM
Write/Read Data Byte ( command 1,2 ) operations access display buffer RAM based on Page Address (PA)
register and Column Address (CA) register. To minimize bus interface cycles, PA and CA will be
incremented automatically depending on the setting of Access Control (AC) registers. PA and CA can also
be programmed directly by issuing Set Page Address and Set Column Address commands.
If Wrap-Around (WA) is OFF (AC[0] = 0), CA will stop increasing after reaching the end of page (MC), and
system programmers need to set the values of PA and CA explicitly. If WA is ON (AC[0]=1), when CA
reaches end of page, CA will be reset to 0 and PA will be increased or decrease by 1, depending on the
setting of Page Increment Direction (PID, AC[2]). When PA reaches the boundary of RAM (i.e. PA = 0 or 15),
PA will be wrapped around to the other end of RAM and continue.
(3) Get Status
Action
Get Status
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0 1 BZ MX DE RS WA GN1 GN0 1
Status flag definitions:
BZ: Busy with internal process. When BZ=1 host interface can access if RS=0.
MX: Status of register LC[1], mirror X.
DE: Display enable flag. DE=1 when display enabled
RS: Reset in progress. If RS=1.host interface will be inaccessible.
WA: status of register AC[0] .automatic column/page wrap around.
GN0,1:GN[1:0] .register Gain
(4) Set Column Address
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Column Address LSB CA[3:0] 0 0 0 0 0 0 CA3 CA2 CA1 CA0
Set Column Address MSB CA[7:4] 0 0 0 0 0 1 CA7 CA6 CA5 CA4
Set the SRAM column address before Write/Read memory from host interface.
CA possible value=0-239
10
Revision 0.52
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