UC1608XFAC 데이터 시트보기 (PDF) - Unspecified

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UC1608XFAC

128x240 Matrix LCD Controller-Drivers

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UC1608

128x240 Matrix LCD Controller-Drivers

LCD DISPLAY CONTROLS

CLOCK & TIMING GENERATOR

UC1608 contains a built-in system clock. All

required components for the clock oscillator are

built-in. No external parts are required.

DRIVER MODES

COM and SEG drivers can be in either Idle mode

or Active mode, controlled by Display Enable flag

(DC[2]). When COM drivers are in idle mode, their

outputs are high-impedance (open circuit). When

SEG drivers are in idle mode, their outputs are

connected to VSS.

DRIVER ARRANGEMENTS

The naming conventions are: COM(x), where

x=1~128, refers to the COM driver for the x-th row

of pixels on the LCD panel.

The mapping of COM(x) to LCD pixel rows is the

same for all MR, MX and MY settings. When MR is

not 128, then COM(x) ~ COM128 (X = MR+1)

should be left open circuit.

DISPLAY CONTROLS

There are three groups of display control flags in

the control register DC: Driver Enable (DE), All-

Pixel-ON (APO) and Inverse (PXV). DE has the

overriding effect over PXV and APO.

DRIVER ENABLE (DE)

Driver Enable is controlled by the value of DC[2].

When DE is set to OFF (logic “0”), both SEG and

COM drivers will become idle and UC1608 will put

itself into Sleep mode to conserve power.

When DE is set to ON, UC1608 will first exit from

Sleep mode, restore the power (VLCD, VBIAS etc.)

and then turn on COM and SEG drivers.

ALL PIXELS ON (APO)

When set, this flag will force all active SEG drivers

to output On signals, disregarding the data stored

in the display buffer.

This flag has no effect when Display Enable is OFF

and it has no effect on data stored in RAM.

INVERSE (PXV)

When this flag is set to ON, active SEG drivers will

output the inverse of the value it received from the

display buffer RAM (bit-wise inversion). This flag

has no impact on data stored in RAM.

SCROLLING

SL register can be used to implement scroll

function. Setting SL to a non-zero value N will

result in the image being scrolled by N lines.

ITO LAYOUT CONSIDERATIONS FOR COM SIGNALS

Since UC1608 line rate is as fast as 10KHz and the

common scanning pulse is only 100us wide, it is

critical to minimize the RC delay experienced by

common electrodes.

It is recommended to optimize the ITO layout to

limit the worst case common electrode RC delay as

calculated below:

(RROW/3 + RCOM + ROUT) x CROW < 2uS

where

CROW: LCD loading capacitance of one row

of pixels.

RROW: ITO resistance over one row of

pixels within the active area

RCOM: ITO resistance leading from COF

OLD to the active area

ROUT: UC1608 output, 1.5K Ohm typical

(Revision 0.52 Preview)

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