IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

PSRout[7-0]

This bus outputs the data from the last programma-

ble shift register in the chain. The data on this bus

is synchronously clocked by the rising edge of CLK.

In a cascade arrangement this port will be con-

nected to the PSRin port of the next device. At

power up, or after a reset, the PSRout pins are

tristated. They are enabled by SCR[5].

Cin[21-0]

The Cascade Input port allows IMSA110s to be

cascaded. It also can be used for combining an

external signal (e.g. a reference image or an offset)

with the processed result. In a cascade arrange-

ment, this bus will be connected to the Cascade

Output of the previous device. The data on the Cin

bus is sampled on the rising edge of CLK.

Cout[21-0]

This bus outputs the processed result from the

IMSA110 and can also be used for cascading. The

22-bit result is synchronously clocked by the rising

edge of CLK. In a typical cascaded system this bus

will be connected to the Cascade Input port of the

next device. On the last device in the cascade, this

bus will be the output of the overall system. At

power up, or after a reset, the Cout pins are tris-

tated. They are enabled by SCR[4].

8.3 Asynchronous input/output

E1, E2

If both of these signals are low, then the microproc-

essor interface is enabled. The operation of these

enable signals is very similar to those found on

static RAMs. When either of these signals are high

the Write Enable and the address inputs are ig-

nored and the microprocessor interface Data sig-

nals are high impedance. When both Enable sig-

nals are low a read or write access is made to

registers or the RAMs within the IMSA110. Access

to the microprocessor interface can occur asyn-

chronously to the synchronous pins (PSRin,

PSRout, Cin, Cout) of the device.

W

Write Enable indicates whether the access to the

IMS A110 memory interface is to be a read or a

write. If W is low a write access is indicated.

ADR[8-0]

The nine bit binary value applied to the address

inputs of the IMSA110 indicates which register or

RAM location within the device is to be accessed.

D[7-0]

During a write to the microprocessor interface an

8-bit word is applied to the Data pins which is

written to the appropriate location. During a read

cycle the contents of the location accessed are

placed on the Data pins. When either of the En-

ables are high the Data pins are high impedance.

9 REGISTER DESCRIPTION

Memory map

Within the IMSA110 addresses are fully decoded.

Reading from locations not defined in the memory

map will produce zero data. Data written to such

locations is ignored. This allows the part to be fully

programmed using a ROM with an address incre-

meter. In this case, for future compatibility, zero

should be written to all undefined locations.

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