IMSA110 데이터 시트보기 (PDF) - STMicroelectronics
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IMSA110 Datasheet PDF : 26 Pages
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IMSA110
Continous bank swap SCR[0]
Default: 0
The continuous bank Swap bit selects whether the
the two banks of coefficient registers are used
alternately after each data input or if this is control-
led solely by the state of the ‘Current Bank’ bit in the
Active Control Register ACR[0].
SCR[0]
0
1
Swap mode
Swap on asserting ACR[0] *
Swap after end of each input cycle
10.3 Active control register (ACR)
Reserved
ACR[7-2]
Default: 00000
These 6 most significant bits of the ACR are re-
served. The user should write zero to these loca-
tions to maintain compatibility with future products.
The value read from these locations will be zero.
Enable look up table ACR[1]
Default: 0
Writing a zero into this control bit allows the memory
interface to access the Look up table; the output to
the data transformation unit will be zero. The nor-
maliser will be controlled by BCR3[7-3], regardless
of the state of BCR3[2]. Writing a one to ACR[1]
allows the IMS A110 to use the Look up Table. After
changing this bit, 2 clock cycles must occur before
the Look up Table can be accessed.
ACR[1]
0
1
LUT mode
Memory interface access *
Data transformation unit
Current bank
ACR[0]
Default: 0
When the ‘Continuous Bank Swap’ bit is set to zero,
writing a zero into this control bit instructs the IMS
A110 to use the set of coefficient registers at ad-
dresses 0 to #X26. Setting a one to this bit instructs
the IMS A110 to use the set of coefficient registers
at addresses #40 to #X66. If the ‘Continuous Bank
Swap’ bit is set to one, then this bit only indicates
the bank selected for the first cycle of the continu-
ous swap mode. Writing to this bit whilst in continu-
ous bank swap mode (SCR[0]=1) will result in
undefined behaviour of the mac array.
ACR[0]
0
1
Coefficient bank
Use coefficient registers at 0 to #X26 *
Use coefficient registers at #40 to #X66
10.4 Backend control register 0 (BCR0)
Enable full-wave
rectification
BCR0[7]
Default: 0
If this bit is set the output of the cascade adder is
full-wave rectified (absolute value operation) be-
fore it is fed to the remainder of the backend. This
bit will override the function of the BCR0[6].
Enable half-wave
rectification
BCR0[6]
Default: 0
Writing a one in this bit will cause the negative
values from the cascade adder to be replaced with
zero. Note that writing a one into BCR0[7] will
override the function of this control bit.
BCD0[7-6]
00
01
10
11
Rectifier mode
Straight through *
Half wave rectification
Full wave rectification
Full wave rectification
Mac array output
scaler
BCR0[5-1] Default: 00000
The contents of these five bits control the amount
of right or left shift applied to the data at the output
of the mac array. This field is interpreted as a two’s
complement number. A positive number repre-
sents a right shift (divide). Any shift in the range -8
(11000) to +8 (01000) is legal. Values outside this
range will result in undefined behaviour of the mac
output scaler.
Zero cascade input BCR0[0]
Default: 0
This bit controls the Cascade Input Multiplexer.
Writing a one to this bit will cause a zero, instead of
the cascade input data, to be fed to the cascade
adder.
BCR[0]
0
1
Cascade input mode
Cascade data *
Zero
10.5 Backend control register 1 (BCR1)
Reserved
BCR1[7-2] Default: 00000
These locations are reserved. The user should
write zero to these locations to maintain compati-
bility with future products. The values read from
these locations will be zero.
Static threshold
BCR1[1]
Default: 0
If this bit is set to one, the signals from the compa-
rator will be used to increment the Over / Under-
shoot Counter only. If this bit is zero, the signals
from the comparator will be used to latch the output
of the Cascade Adder into the Maximum / Minimum
Register (MMR), and to increment the counter. In
this case the counter will have been incremented
by the number of times that the threshold has been
updated.
19/26
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