IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

Figure 7 : IMSA110 Memory Map

Address

bit

Name

(Hex)

7

6

5

4

3

2

1

0

1FF

LUT

Look Up Table

100

0FC-0FF

0F8-0FB

0D0

0BC

0B8-0BA

0B4

0B0-0B2

LSR

USR

TCR

COU

OUB

CMM

MMB

0A3

BCR3

0A2

BCR2

0A1

BCR1

0A0

BCR0

092

ACR

090

SCR

085

PCRC

084

PCRC

083

PCRB

082

PCRB

081

PCRA

080

PCRA

066

...

CR1c

060

Lower Saturation Register

Upper Saturation Register

0

0

Full

Wave

0

0

0

0

0

Copy Over/UnderShoot Buffer

Over/UnderShoot Buffer

Copy Min/Max Buffer

Min/Max Buffer

Normaliser Control

Dynamic LUT to

normali- output

0

sation

adder

LS

output

byte

MS

output

byte

Look Up Prescaler

0

0

0

0

0

Static Greater

threshold Than

Half

Wave

MAC Output Scaler

Zero

Cascade

0

0

0

0

0

Backend

LUT

Access

Current

Bank

PosLUT

Addr

PSR Out

Enable

Cascade

Enable

Unsigned

Coef

Load

Unsigned

Data

Bypass

PSRs

Cont

Swap

0

0

0

0

Shift Length (Upper Bits)

Shift Length (Lower Bits)

0

0

0

0

Shift Length (Upper Bits)

Shift Length (Lower Bits)

0

0

0

0

Shift Length (Upper Bits)

Shift Length (Lower Bits)

Bank 1 Coefficient Register

056

...

CR1b

050

Bank 1 Coefficient Register

046

...

CR1a

040

Bank 1 Coefficient Register

026

...

CR0c

020

Bank 0 Coefficient Register

016

...

CR0b

010

Bank 0 Coefficient Register

006

...

CR0a

000

Bank 0 Coefficient Register

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