IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

OUB

Overshoot/undershoot buffer

These three memory locations hold a 22-bit word,

with the least significant byte at the lowest address,

and act as a buffer between the OUC and the

microprocessor interface. All the transactions be-

tween the OUC and the host processor must take

place through this register. When the OUC is not in

use, the value of this buffer is undefined.

COU

Copy OUC

This location in the memory is used to enable the

data transfer between the OUB and OUC. A write

to this location causes the contents of OUB to be

copied into the OUC. A read from this location

causes the reverse, i.e the contents of the OUC are

copied into the OUB. The value written to this

location is ignored, the value read back will be

undefined.

TCR

Test control register

This register is used for testing, and should be

loaded with zero for normal operation.

USR

Upper saturation register

This is a 32-bit value with the least significant byte

at the lowest address. Its contents are used to

replace the LUT output if positive overflow(s) occur

in the look up prescaler and / or in the cascade

adder. Accesses from the microprocessor interface

can only be made while ACR[1] is set to zero.

LSR

Lower saturation register

This is a 32-bit value with the least significant byte

at the lowest address. Its contents are used to

replace the LUT output if negative overflow(s) occur

in the look up prescaler and / or in the cascade

adder. Accesses from the microprocessor interface

can only be made while ACR[1] is set to zero.

LUT

Look up table

These locations are for the 256-byte look up table

which is used for data mapping and transformation

operations. From the microprocessor interface,

these locations are addressed in the same way as

that seen by the 8-bit output of look up prescaler.

When used in 32 bit mode, the locations are treated

in the same way as other 32 registers: Word 0 has

its most significant byte at #103, its least significant

byte at #100, Word 12 has its most significant byte

at #133, its least significant byte at #130. Accesses

from the microprocessor interface can only be

made while ACR[1] is set to zero.

10. REGISTERS — BIT ALLOCATION

This section describes the register details bit by bit.

Each section commences with the name of the

register with the bit number(s) followed by the de-

fault value, in the general format:

Name REGISTER [MSB—LSB] Default : MSB...LSB

The least significant bit of a register is bit 0.

* in the tables indicates the default state of the

register bit(s).

10.1 PSR control registers (PCR)

PSRA control

PCRA[10-0] Default: 0… 0

These eleven least significant bits of the PCRA are

used to specify the length of the last Programmable

Shift Register (PSRA). The length of the shift reg-

ister will be numerically equal to the binary value

loaded in these bits. The value loaded in must be

in the range of 0 to 1120 decimal. If a value outside

this range is written to these bits the behaviour of

the shift register will be undefined. After updating

this register, the behaviour of the delay is undefined

for 22 clock cycles. Hence changing the length from

1000 to 1001 delays, will result in correct output

only after 1023 cycles. This will also have to propa-

gate through the backend before the cascade out-

put values will be correct.

Reserved

PCRA[15-11] Default: 00000

These 5 most significant bits of the PCRA are

reserved. The user should write zero to these loca-

tions to maintain compatibility with future products.

The value read from these locations will be zero.

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