IMSA110 데이터 시트보기 (PDF) - STMicroelectronics
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IMSA110 Datasheet PDF : 26 Pages
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IMSA110
CR0c
Coefficient registers bank 0c
These seven 8-bit locations contain coefficients
which can be used by the first, of the three, 7-stage
mac arrays in the chain. CR0c(0) (address #020)
corresponds to the coefficient register of this mac
array nearest to its output. Similarly CR0c(6) (ad-
dress #026) corresponds to to the coefficient regis-
ter of this mac nearest to its input. Their behaviour
is otherwise identical to CR0a.
CR1a
Coefficient registers bank 1a
These seven 8-bit locations contain coefficients
which can be used by the third, of the three, 7-stage
mac arrays in the chain. CR1a(0) (address #040)
corresponds to the coefficient register of this mac
array nearest to its output. Similarly CR1a(6) (ad-
dress #046) corresponds to to the coefficient regis-
ter of this mac nearest to its input. These registers
will be used provided that ACR[0], ‘Current Bank’ is
set to one, or continuous bank swap mode is in
operation (SCR[0] set to one).
CR1b
Coefficient registers bank 1b
These seven 8-bit locations contain coefficients
which can be used by the second, of the three,
7-stage mac arrays in the chain. CR1b(0) (address
#050) corresponds to the coefficient register of this
mac array nearest to its output. Similarly CR1b(6)
(address #056) corresponds to to the coefficient
register of this mac nearest to its input. Their be-
haviour is otherwise identical to CR1a.
CR1c
Coefficient registers bank 1c
These seven 8-bit locations contain coefficients
which can be used by the second, of the three,
7-stage mac arrays in the chain. CR1c(0) (address
#060) corresponds to the coefficient register of this
mac array nearest to its output. Similarly CR1c(6)
(address #066) corresponds to to the coefficient
register of this mac nearest to its input. Their be-
haviour is otherwise identical to CR1a.
PCRA
PSRA Control register
This is a 16-bit register, with least significant byte
at location #080, and is used to set up the length of
the last shift register in the chain. Programmed
lengths outside the range 0 to 1120 will cause
undefined behaviour of the shift register.
PCRB
PSRB Control register
This is a 16-bit register, with least significant byte
at location #082, and is used to set up the length of
the second shift register in the chain. Programmed
lengths outside the range 0 to 1120 will cause
undefined behaviour of the shift register.
PCRC
PSRC Control register
This is a 16-bit register, with least significant byte
at location #084, and is used to set up the length of
the first shift register in the chain. Programmed
lengths outside the range 0 to 1120 will cause
undefined behaviour of the shift register.
SCR
Static control register
The Static Control Register contains the control bits
which set up parts of the IMS A110 which are likely
to not need reconfiguration during processing. The
contents of this register are not affected by the IMS
A110 and can be read at any time. Modifying the
Static Control register during processing will result
in undefined behaviour. Normal operation will start
to occur between 0 and 3 clock cycles after the
completion of the write cycle.
ACR
Active control register
The Active Control Register contains status and
control bits which are likely to be accessed during
normal operation of the IMS A110.
BCR
Backend configuration register
The Backend Configuration Registers consist of
four byte-wide registers BCR0, BCR1, BCR2, and
BCR3 which are located at addresses #0A0, #0A1,
#0A2, and #0A3 respectively. These four registers
are used to control the backend post-processing
unit. None of the control bits in these registers can
be modified by the IMS A110. Modification of the
values in these registers during processing may
result in undefined behaviour. Normal operation will
start to occur between 0 and 3 clock cycles after the
completion of the write cycle.
MMB
Maximum/minimum buffer
These three locations hold a 24-bit wide word, with
the least significant byte at the lowest address, and
act as a buffer between the MMR and the micro-
processor interface. All the transactions between
the MMR and the host processor must take place
through this register. When the MMR is not in use,
the value of this buffer is undefined.
CMM
Copy MMR
This location is used to enable the data transfer
between the MMB and MMR. A write to this location
causes the contents of MMB to be copied into the
MMR and bits 23 and 22 of the MMR (the cascade
adder overflow flags) to be set to zero. A read from
this location causes the reverse, i.e the contents of
the MMR are copied into the MMB. The value
written to this location is ignored, the value read
back is undefined.
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