AT90PWM81
3.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3-2. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
7
0
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them
are single cycle instructions.
As shown in Figure 3-2, each register is also assigned a data memory address, mapping them directly into
the first 32 locations of the user Data Space. Although not being physically implemented as SRAM loca-
tions, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-
pointer registers can be set to index any register in the file.
3.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-
bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and
Z are defined as described in Figure 3-3.
Figure 3-3. The X-, Y-, and Z-registers
15
XH
XL
0
X-register
7
07
0
R27 (0x1B)
R26 (0x1A)
15
YH
YL
0
11
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