MT28F002B3 데이터 시트보기 (PDF) - Micron Technology
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MT28F002B3 Datasheet PDF : 31 Pages
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2Mb
SMART 3 BOOT BLOCK FLASH MEMORY
a null WRITE. To execute a null WRITE, FFH must be
written when BYTE# is LOW, or FFFFH must be written
when BYTE# is HIGH. Once the ISM status bit (SR7) has
been set, the device will be in the status register read
mode until another command is issued.
ERASE SEQUENCE
Executing an ERASE sequence will set all bits within
a block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To
provide added security against accidental block era-
sure, two consecutive command cycles are required to
initiate an ERASE of a block. In the first cycle, addresses
are “Don’t Care,” and ERASE SETUP (20H) is given. In
the second cycle, VPP must be brought to VPPH, an
address within the block to be erased must be issued,
and ERASE CONFIRM (D0H) must be given. If a com-
mand other than ERASE CONFIRM is given, the write
and erase status bits (SR4 and SR5) will be set, and the
device will be in the status register read mode.
After the ERASE CONFIRM (D0H) is issued, the ISM
will start the ERASE of the addressed block. Any READ
operation will output the status register contents on
DQ0-DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1). Once the ERASE is completed, the
device will be in the status register read mode until
another command is issued. Erasing the boot block also
requires that either the RP# pin be set to VHH or the WP#
pin be held HIGH at the same time VPP is set to VPPH.
ERASE SUSPENSION
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command
allows other commands to be executed while pausing
the ERASE in progress. Once the device has reached the
erase suspend mode, the erase suspend status bit (SR6)
and ISM status bit (SR7) will be set. The device may now
be given a READ ARRAY, ERASE RESUME or READ
STATUS REGISTER command. After READ ARRAY has
been issued, any location not within the block being
erased may be read. If ERASE RESUME is issued before
SR6 has been set, the device will immediately proceed
with the ERASE in progress.
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP (SR3),
write (SR4) and erase (SR5) status bits may be checked. If
one or a combination of these three bits has been set, an error
has occurred. The ISM cannot reset these three bits. To
clear these bits, CLEAR STATUS REGISTER (50H) must be
given. If the VPP status bit (SR3) is set, further WRITE or
ERASE operations cannot resume until the status register is
cleared. Table 4 lists the combination of errors.
Table 4
Status Register Error Decode1
STATUS BITS
SR5 SR4 SR3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ERROR DESCRIPTION
No errors
VPP voltage error
WRITE error
WRITE error, VPP voltage not valid at time of WRITE
ERASE error
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
Command sequencing error or WRITE/ERASE error
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
2Mb Smart 3 Boot Block Flash Memory
F48.p65 – Rev. 1/00
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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