MT28F002B3 데이터 시트보기 (PDF) - Micron Technology

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MT28F002B3

2Mb SMART 3 BOOT BLOCK FLASH MEMORY

Micron Technology 

2Mb

SMART 3 BOOT BLOCK FLASH MEMORY

SELF-TIMED BLOCK ERASE SEQUENCE1

Start

COMPLETE BLOCK ERASE

STATUS-CHECK SEQUENCE

Start (ERASE completed)

WRITE 20H

VPP = 3.3V or 5V

WRITE D0H,

Block Address

STATUS REGISTER

READ

NO

SR7 = 1?

YES

Complete Status2

Check (optional)

ERASE Complete 3

NO

Suspend ERASE?

YES

Suspend 4

Sequence

ERASE Resumed

SR3 = 0?

NO

YES

SR4, 5 = 1?

YES

NO

SR5 = 0?

NO

VPP Error5, 6

Command Sequence Error6

BLOCK ERASE Error6

YES

ERASE Successful

NOTE: 1. Sequence may be repeated to erase additional blocks.

2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is

cleared.

3. To return to the array read mode, the FFH command must be issued.

4. Refer to the ERASE SUSPEND flowchart for more information.

5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE

or ERASE operations are allowed by the CEL.

6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

2Mb Smart 3 Boot Block Flash Memory

F48.p65 – Rev. 1/00

16

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

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