MT28F002B3 데이터 시트보기 (PDF) - Micron Technology

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MT28F002B3

2Mb SMART 3 BOOT BLOCK FLASH MEMORY

Micron Technology 

2Mb

SMART 3 BOOT BLOCK FLASH MEMORY

SELF-TIMED WRITE SEQUENCE

(WORD or BYTE WRITE)1

COMPLETE WRITE STATUS-CHECK

SEQUENCE

Start

Start (WRITE completed)

WRITE 40H or 10H

VPP = 3.3V or 5V

WRITE Word or Byte

Address/Data

SR3 = 0?

YES

NO VPP Error4, 5

SR4 = 0?

YES

NO BYTE/WORD WRITE Error5

WRITE Successful

STATUS REGISTER

READ

SR7 = 1?

NO

YES

Complete Status2

Check (optional)

WRITE Complete 3

NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.

2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is

cleared.

3. Device will be in status register read mode. To return to the array read mode, the FFH command must be issued.

4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE

or ERASE operations are allowed by the CEL.

5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

2Mb Smart 3 Boot Block Flash Memory

F48.p65 – Rev. 1/00

15

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

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