DJLXT971ALC.A4 데이터 시트보기 (PDF) - Intel

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DJLXT971ALC.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Figure 1. LXT971A Block Diagram

RESET

ADDR<4:0>

MDIO

MDC

MDINT

MDDIS

TX_EN

TXD<3:0>

TX_ER

TX_CLK

LED/CFG<3:1>

COL

RX_CLK

RXD<3:0>

RXDV

CRS

RX_ER

Management /

Mode Select

Logic

Register Set

Clock

Generator

Power Supply

Parallel/Serial

Converter

Manchester

Encoder

10

Scrambler 100

& Encoder

Register

Set

Auto

Negotiation

OSP™

Pulse

Shaper

Collision

Detect

Clock

Generator

Media

Select

Serial-to-

Parallel

Carrier Sense Converter

Data Valid

Error Detect

Manchester

10 Decoder

100

Decoder &

Descrambler

OSP™

Slicer

+

TP

Driver

-

+

ECL

Driver

-

TP/Fiber

Out

OSP™

Adaptive EQ with

Baseline Wander

Cancellation

JTAG

+

100TX

-

+

100FX

-

+

10BT

-

TP/Fiber In

VCC

GND

PWRDWN

REFCLK

TxSLEW<1:0>

TPFOP

TPFON

TDIO

5

TMS

TCK

TRST

TPFIP

TPFIN

SD/TP

Datasheet

11

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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