MT46H16M16 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M16

Mobile DDR SDRAM

Micron Technology 

256Mb: x16, x32 Mobile DDR SDRAM

Register Definition

Figure 9:

CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the

clock stop mode. One clock cycle and at least one NOP or DESELECT is required after

the clock is restarted before a valid command can be issued. Figure 9 on page 21 illus-

trates the clock stop mode.

Clock Stop Mode

CK#

CK

CKE

Ta1

((

))

((

))

((

))

((

Command

))

((

))

((

Address

))

((

))

DQ, DQS

(High-Z)

((

))

NOP1

Ta2

CMD2

Valid

Exit clock stop mode

Tb3

Tb4

((

((

))

))

((

((

))

))

((

))

((

))

((

))

( ( CMD2

))

NOP

((

))

NOP

((

))

((

((

))

((

Valid

))

((

))

))

((

))

((

((

))

))

All DRAM activities

must be complete

Enter clock stop mode

Don’t Care

Notes:

1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before

any valid command is issued.

2. Any valid command is allowed; device is not in clock stop mode.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

21

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2005 Micron Technology, Inc. All rights reserved.

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