MT46H16M16 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M16

Mobile DDR SDRAM

Micron Technology 

256Mb: x16, x32 Mobile DDR SDRAM

Timing Diagrams

Figure 44: Self Refresh Mode

CK#

CK1

CKE1

Command4

Address

DQS

DQ

DM

T0

T1

((

))

((

tCH tCL

))

tIS tIH

tIS

tIS tIH

NOP

tRP2

((

))

((

))

AR

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

Enter self refresh mode

Ta01

tCK

Ta1

tIS

NOP

Tb0

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

tXSR3

VALID

tIS tIH

VALID

Exit self refresh mode

Don’t Care

Notes:

1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3. NOPs or DESELECT is required for tXSR time with at least two clock pulses.

4. AR = AUTO REFRESH command.

5. CKE must remain LOW to remain in self refresh mode.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

72

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2005 Micron Technology, Inc. All rights reserved.

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