MT46H16M16 데이터 시트보기 (PDF) - Micron Technology
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MT46H16M16 Datasheet PDF : 79 Pages
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
8. Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details.
Figure 46: Bank Read – with Auto Precharge
T0
T1
T2
T3
T4
T5 T5n T6 T6n T7
T8
CK#
CK
tIS tIH
tCK
tCH tCL
CKE
tIS tIH
Command5
NOP6
ACT
NOP6
READ2
NOP6
NOP6
NOP6
NOP6
ACT
tIS tIH
A0–A9
RA
Col n
RA
A11, A12
A10
BA0, BA1
DM
RA
RA
tIS tIH
Bank x
tRCD
tRAS
tRC
3
tIS tIH
Bank x
RA
RA
Bank x
tRP
Case 1: tAC (MIN) and tDQSCK (MIN)
DQS
DQ1
CL = 2
tRPRE
tDQSCK (MIN)
tRPST
tLZ (MIN)
tAC (MIN)
DOUT
n
tLZ (MIN)
DOUT
n+1
DOUT
n+2
DOUT
n+3
Case 2: tAC (MAX) and tDQSCK (MAX)
DQS
tRPRE tDQSCK (MAX)
tRPST
DQ1
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
tAC (MAX)
tHZ (MAX)
Transitioning data
Don’t Care
Notes:
1. DOUT n = data-out from column n.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
74
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©2005 Micron Technology, Inc. All rights reserved.
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