MT9160AN1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9160AN1

ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)

Zarlink Semiconductor Inc 

MT91L60/61

Data Sheet

When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on

DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high.

Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state.

When low, data transmission is halted and this timeslot is tri-stated on DSTo.

B1-Channel and B2-Channel

Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and

transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel

(Control Register 1, address 03h) are used for this purpose.

If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR

control bits, Control Register 1 address 03h).

IRQ

Microport Read/Write Access

FP

n-3

n-2

n-1

n

n+1

n+2

n+3

n+4*

DSTo/

DSTi

Di-bit Group

Receive

D-Channel

I

D0

II

III

IV

D1 D2

D3 D4

D5 D6

D7

No preset value

Di-bit Group

I

Transmit D0

D-Channel

II

III

IV

D1 D2

D3 D4

D5 D6

D7

Power-up reset to 1111 1111

* note that frame n+4 is equivalent to frame n of the next cycle.

Figure 7a - D-Channel 16 kb/s Operation

FP

C4i

C2

DSTo/

DSTi

IRQ

D0

8 kb/s operation

D1

tif =500 nsec max

16 kb/s operation

Microport Read/Write Access

Figure 7b - IRQ Timing Diagram

tir =500 nsec max

Rpullup= 10 k

Reset coincident with

Read/Write of Address 04 Hex

or next FP, whichever occurs first

11

Zarlink Semiconductor Inc.

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