MT48H16M16LFF-8 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT48H16M16LFF-8

256Mb: x16 MOBILE SDRAM

Micron Technology 

ADVANCE

256Mb: x16

MOBILE SDRAM

This is shown in Figure 7 for CAS latencies of two and

three; data element n + 3 is either the last of a burst of

four or the last desired of a longer burst. The 256Mb

SDRAM uses a pipelined architecture and therefore

does not require the 2n rule associated with a prefetch

architecture. A READ command can be initiated on any

clock cycle following a previous READ command. Full-

speed random read accesses can be performed to the

same bank, as shown in Figure 8, or each subsequent

READ may be performed to a different bank.

Figure 7

Consecutive READ Bursts

T0

T1

T2

T3

CLK

T4

T5

COMMAND

READ

NOP

NOP

ADDRESS

BANK,

COL n

NOP

READ

NOP

X = 0 cycles

BANK,

COL b

DQ

DOUT

n

CAS Latency = 1

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

ADDRESS

BANK,

COL n

X = 1 cycle

BANK,

COL b

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

CAS Latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL b

X = 2 cycles

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

DOUT

n+3

DOUT

b

DON’T CARE

256Mb: x16 Mobile SDRAM

MobileRamY26L_A.p65 – Pub. 5/02

16

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

Share Link: