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MT46H16M16

Mobile DDR SDRAM

Micron Technology

MT46H16M16 Datasheet PDF : 79 Pages

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256Mb: x16, x32 Mobile DDR SDRAM

General Description

Table 4: 90-Ball VFBGA Ball Description

Ball Numbers

G2, G3

Symbol

CK, CK#

CKE

CS#

G9, G8, G7

K8, K2, F8, F2

RAS#, CAS#,

WE#

DM0–DM3

H8, H9

BA0, BA1

J8, J9, K7, K9, K1, K3,

J1, J2, J3, H1, J7, H2

A0–A11

A12/DNU

R8, P7, P8, N7, N8, M7,

M8, L7, L3, M2, M3,

N2, N3, P2, P3, R2, A8,

B7, B8, C7, C8, D7, D8,

E7, E3, D2, D3, C2, C3,

B2, B3, A2

L8, L2, E8, E2

DQ0–DQ31

DQS0–DQS3

A7, B1, C9, D1, E9, L9,

M1, N9, P1, R7

VDDQ

Type

Input

I/O

Description

Clock: CK is the system clock input. CK and CK# are differential clock

inputs. All address and control input signals are sampled on the

crossing of the positive edge of CK and the negative edge of CK#. Input

and output data is referenced to the crossing of CK and CK# (both

directions of the crossing).

Clock enable: CKE HIGH activates and CKE LOW deactivates the

internal clock signals, input buffers, and output drivers. Taking CKE

LOW enables PRECHARGE power-down and SELF REFRESH operations

(all banks idle) or ACTIVE power-down (row active in any bank). CKE is

synchronous for all functions except SELF REFRESH exit. All input

buffers (except CKE) are disabled during power-down and self refresh

modes.

Chip select: CS# enables the command decoder (registered LOW) and

disables the command decoder (registered HIGH). All commands are

masked when CS# is registered HIGH. CS# provides for external bank

selection on systems with multiple banks. CS# is considered part of the

command code.

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the

command being entered.

Input data mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS. Although

DM balls are input-only, the DM loading is designed to match that of

DQ and DQS balls. For the x32, DM0 is DM for DQ0–DQ7; DM1 is DM

for DQ8–DQ15; DM2 is DM for DQ16–DQ23; and DM3 is DM for DQ24–

DQ31.

Bank address inputs: BA0 and BA1 define to which bank an ACTIVE,

READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1

also determine which mode register (standard mode register or

extended mode register) is loaded during a LOAD MODE REGISTER

command.

Address inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A10) for READ or WRITE

commands, to select one location out of the memory array in the

respective bank. During a PRECHARGE command, A10 determines

whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide

the op-code during a LOAD MODE REGISTER command.

A12 is an address input for the LG reduced page-size option (see

“Options” on page 1). Leave as DNU for JEDEC-standard option.

Data input/output: Data bus for x32.

I/O

Supply

Data strobe: Output with read data, input with write data. DQS is

edge-aligned with read data, center-aligned with write data. Data

strobe is used to capture data.

DQ power supply.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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