MT46H16M16 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M16

Mobile DDR SDRAM

Micron Technology 

256Mb: x16, x32 Mobile DDR SDRAM

Register Definition

7. Using the LOAD MODE REGISTER command, load the standard mode register as

desired.

8. Issue a NOP or DESELECT command for at least tMRD time.

9. Using the LOAD MODE REGISTER command, load the extended mode register to the

desired operating modes. Note that the sequence in which the standard and extended

mode registers are programmed is not critical.

10. Issue NOP or DESELECT commands for at least tMRD time.

The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid

command.

Register Definition

Mode Registers

The mode registers are used to define the specific mode of operation of the Mobile DDR

SDRAM. Two mode registers are used to specify the operational characteristics of the

device.

Standard Mode Register

The standard mode register bit definition enables the selection of burst length, burst

type, CAS latency, and operating mode, as shown in Figure 6 on page 16. Reserved states

should not be used, as this may result in setting the device into an unknown state or

cause incompatibility with future versions of Mobile DDR SDRAM. The standard mode

register is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and

BA1 = 0) and will retain the stored information until it is programmed again, the device

goes into deep power-down mode, or the device loses power.

Reprogramming the mode register will not alter the contents of the memory, provided it

is performed correctly. The mode register must be loaded when all banks are idle and no

bursts are in progress, and the controller must wait before initiating the subsequent

operation. Violating any of these requirements will result in unspecified operation.

Burst Length

Read and write accesses to the Mobile DDR SDRAM are burst oriented; the burst length

is programmable. The burst length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or

8 locations are available for both sequential and interleaved burst types.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst will wrap when a boundary is reached. The block is uniquely

selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when BL = 8, where

Ai is the most significant column address bit for a given configuration. The remaining

(least significant) address bits are used to specify the starting location within the block.

The programmed burst length applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed either to be sequential or interleaved

via the standard mode register.

The ordering of accesses within a burst is determined by the burst length, the burst type,

and the starting column address (see Table 5 on page 17).

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2005 Micron Technology, Inc. All rights reserved.

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